Spin Semiconductor

Posted: **Thu Jun 12, 2025 4:35 am**

According to the coding examples article:

http://www.spinsemi.com/knowledge_base/ ... ngle_waves

skp	run,1		;establish LFO on first sample cycle only
wldr	rmp0,10,4096  	;set values for rate and range
cho	rdal,rmp0	;read LFO saw wave, accumulator value will range from 0 to 0.5
sof	1,-0.25		;offset by -0.25, giving a saw wave that ranges from -0.25 to +0.25
absa  	 		;make negative values positive, making the result a triangle.

Is the value outputted by the CHO RDAL dependent on the ramp range such that:
4096 : [0 to 0.5] range output
2048 : [0 to 0.25] range output
1024 : [0 to 0.125] range output
512 : [0 to 0.0625] range output

If I wanted to keep track of the RPTR2 (address + half ramp). Would this be sufficient?

Code: Select all

skp	run,1		;establish LFO on first sample cycle only
wldr	rmp0,10,4096  	;set values for rate and range
cho	rdal,rmp0	;read LFO saw wave, accumulator value will range from 0 to 0.5
sof 	1, -0.25 	; - 0.25
skp 	GEZ, 1 		; if negative : 
sof	1, 0.5 		; + 0.5

Posted: **Thu Jun 12, 2025 7:26 am**

knutolai wrote: ↑Thu Jun 12, 2025 4:35 am If I wanted to keep track of the RPTR2 (address + half ramp). Would this be sufficient?

Depends, the ramp you read is just the offset and in the chorus hardware is added to the address supplied so no it is not sufficient if you need to track the actual address. It is if you are just tracking the relative offset.

But (there is always a condition) it is if the block of memory you are using is defined in the 0-4096 range, SpinAsm allocates memory as it encounters mem statements so if it is the first block defined then it will start at address 0.

Posted: **Thu Jun 12, 2025 3:24 pm**

Im sorry that comment should have read "value + half ramp" or something unrelated to delay memory. I'm asking about the ramps in isolation. Not their relation to delay memory addresses.

To rephrase I'm looking for the value ranges the CHO RDAL instruction adds to ACC. Are the ranges I listed correct?

Posted: **Thu Jun 12, 2025 3:35 pm**

I believe they are correct, been many years since I looked at the schematic or layout.

Spin Semiconductor

CHO RDAL output range

CHO RDAL output range

Re: CHO RDAL output range

Re: CHO RDAL output range

Re: CHO RDAL output range